Method of fabricating semiconductor package

ABSTRACT

A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Korean Patent Application No.10-2013-0020632 filed on Feb. 26, 2013 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present inventive concept relates to a method of fabricating asemiconductor package.

2. Description of the Related Art

One of the major challenges in the semiconductor industry is tofabricate small, multi-function, high-capacity and highly reliableproducts at low costs. One of the most important technologies that makeit possible to achieve such a complex goal is semiconductor packagetechnology. Of package technologies, a chip-stacked semiconductorpackage in which a plurality of chips are stacked is being suggested asa way to achieve the above complex goal.

SUMMARY OF THE INVENTION

Features of the present inventive concept provide a method offabricating a semiconductor package at reduced costs and improvedprocess speed.

Additional features and utilities of the present general inventiveconcept will be set forth in part in the description which follows and,in part, will be obvious from the description, or may be learned bypractice of the general inventive concept.

Exemplary embodiments of the present inventive concept provide a methodof fabricating a semiconductor package, the method comprising: providinga wafer which comprises an upper area having through silicon vias (TSVs)and a lower area not having the TSVs; mounting a semiconductor chip onthe upper area of the wafer; forming a passivation layer to apredetermined thickness to cover the semiconductor chip; exposing theTSVs by removing the lower area of the wafer in a state where no supportis attached to the wafer; and exposing a top surface of thesemiconductor chip by partially removing the passivation layer.

Exemplary embodiments of the present inventive concept also provide amethod of fabricating a semiconductor package, the method comprising:providing a wafer which comprises an upper area having TSVs and a lowerarea not having the TSVs; mounting a semiconductor chip on the upperarea of the wafer; forming a passivation layer to a predeterminedthickness to cover the semiconductor chip; exposing the TSVs by removingthe lower area of the wafer in a state where no support is attached tothe wafer; forming bottom pads and bump balls, which are electricallyconnected to the exposed TSVs, on a bottom surface of the wafer; andexposing a top surface of the semiconductor chip by partially removingthe passivation layer.

Exemplary embodiments of the present inventive concept also provide amethod of fabricating a semiconductor package, the method comprising:providing a wafer which comprises a first area having through siliconvias (TSVs) and a second area not having the TSVs; mounting asemiconductor chip on the first area of the wafer, the semiconductorchip being wider than the wafer to extend beyond sides thereof; forminga passivation layer to a predetermined thickness to cover the wafer andexposed portions of the semiconductor chip extending beyond the wafer;and exposing the TSVs by removing the second area of the wafer andcorresponding portion of the passivation layer in a state where nosupport is attached to the wafer.

In an exemplary embodiment, the method may further include formingthrough vias in the remaining passivation layer to be electricallyconnected to power/ground pads of the semiconductor chip when thethrough vias in the first area are being exposed.

In an exemplary embodiment, the method may further include formingconnection terminals to be electrically connected to the exposed TSVs ona bottom surface of the wafer; and forming connection terminals to beelectrically connected to the exposed through vias of the passivationlayer.

In an exemplary embodiment, the mounting of the semiconductor chipcomprises mounting the semiconductor chip in the form of a flip-chip.

In another exemplary embodiment, the wafer may include: top pads whichare electrically connected to the semiconductor chip; and aredistribution layer which electrically connects the TSVs and the toppads through redistribution lines included therein.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other features and utilities of the present generalinventive concept will become apparent and more readily appreciated fromthe following description of the embodiments, taken in conjunction withthe accompanying drawings of which:

FIG. 1 is a flowchart illustrating a method of fabricating asemiconductor package according to an embodiment of the presentinventive concept;

FIGS. 2 through 13 are views illustrating operations of the method offabricating a semiconductor package according to the embodiment of FIG.1;

FIGS. 14 through 17 are views illustrating operations of a method offabricating a semiconductor package according to another embodiment ofthe present inventive concept;

FIGS. 18 and 19 are views illustrating operations of a method offabricating a semiconductor package according to yet another embodimentof the present inventive concept;

FIG. 20 is a schematic diagram illustrating a memory card to whichsemiconductor packages according to embodiments of the present inventiveconcept are applied;

FIG. 21 is a block diagram of an electronic system to whichsemiconductor packages according to embodiments of the present inventiveconcept are applied; and

FIG. 22 is a diagram illustrating an example of an application of theelectronic system of FIG. 21 to a smartphone.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Features and utilities of the present inventive concept and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings. The present inventive concept may, however, beembodied in many different forms and should not be construed as beinglimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete andwill fully convey the concept of the inventive concept to those skilledin the art, and the present inventive concept will only be defined bythe appended claims. In the drawings, the thickness of layers andregions are exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on” or “connected to” another element or layer, it can bedirectly on or connected to the other element or layer or interveningelements or layers may be present. In contrast, when an element isreferred to as being “directly on” or “directly connected to” anotherelement or layer, there are no intervening elements or layers present.Like numbers refer to like elements throughout. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The use of the terms “a” and “an” and “the” and similar referents in thecontext of describing the invention (especially in the context of thefollowing claims) are to be construed to cover both the singular and theplural, unless otherwise indicated herein or clearly contradicted bycontext. The terms “comprising,” “having,” “including,” and “containing”are to be construed as open-ended terms (i.e., meaning “including, butnot limited to,”) unless otherwise noted.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, for example, a first element, afirst component or a first section discussed below could be termed asecond element, a second component or a second section without departingfrom the teachings of the present inventive concept.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this inventive concept belongs. It is noted that theuse of any and all examples, or exemplary terms provided herein isintended merely to better illuminate the inventive concept and is not alimitation on the scope of the inventive concept unless otherwisespecified. Further, unless defined otherwise, all terms defined ingenerally used dictionaries may not be overly interpreted.

FIG. 1 is a flowchart illustrating a method of fabricating asemiconductor package according to an embodiment of the presentinventive concept. FIGS. 2 through 13 are views illustrating operationsof the method of fabricating a semiconductor package according to anembodiment of the present inventive concept. Specifically, FIG. 3 is across-sectional view taken along line III-III′ of FIG. 2, FIG. 5 is across-sectional view taken along line V-V′ of FIG. 4, and FIG. 12 is across-sectional view taken along line XII-XII′ of FIG. 11.

Referring to FIG. 1, a wafer is provided (operation S100). Specifically,referring to FIG. 2, a wafer 10 including a plurality of unit wafers UWis provided. The unit wafers UW may be divided by a scribing line 12 andplaced on the wafer 10.

Referring to FIG. 3, the wafer 10 (or the unit wafers UVV) may include alower area 30, an upper area 40 disposed on the lower area 30, and aredistribution layer 50 disposed on the upper area 40.

In the current embodiment, the upper area 40 of the wafer 10 may includea plurality of through silicon vias (TSVs) 42, and the lower area 30 ofthe wafer 10 may not include the TSVs 42.

Each of the TSVs 42 may include an insulating layer, a seed layer, and aconductive layer formed sequentially. The insulating layer mayelectrically insulate the conductive layer. The insulating layer mayinclude oxide, nitride or oxynitride. Specifically, the insulating layermay include, e.g., silicon oxide, silicon nitride, or siliconoxynitride. The conductive layer may include a conductive material, suchas a metal. Examples of the metal that forms the TSVs 42 may include,but is not limited to, aluminum (Al), gold (Au), beryllium (Be), bismuth(Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), manganese(Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum(Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta),tellurium (Te), titanium (Ti), tungsten (VV), zinc (Zn), and zirconium(Zr).

The insulating layer, the seed layer and the conductive layer that formeach of the TSVs 42 may be formed by, but is not limited to, chemicalvapor deposition (CVD), plasma enhanced CVD (PECVD), high-density plasmaCVD (HDP-CVD), sputtering, metal organic CVD (MOCVD), or atomic layerdeposition (ALD).

The lower area 30 and the upper area 40 of the wafer 10 may be formed ofa semiconductor material or an insulating material. That is, in someembodiments of the present invention, the lower area 30 and the upperarea 40 may include, e.g., silicon, germanium, silicon-germanium,gallium-arsenide (GaAs), glass, ceramic, etc.

The redistribution layer 50 may include a plurality of top pads 56. Thetop pads 56 may be electrically connected to the TSVs 42 byredistribution lines included in the redistribution layer 50. In someembodiments of the present inventive concept, a first interval P1between the top pads 56 may be different from a second interval P2between the TSVs 42. Specifically, the first interval P1 may be smallerthan the second interval P2 as shown in the drawing. The top pads 56 andthe TSVs 42 arranged at different intervals may be independently andelectrically connected to each other by the redistribution linesincluded in the redistribution layer 50.

The redistribution layer 50 may further include an insulating layer inorder for insulation between the redistribution lines included therein.The insulating layer may include oxide, nitride or oxynitride, forexample, silicon oxide, silicon nitride or silicon oxynitride.

The redistribution lines may include, for example, a metal. In someembodiments of the present inventive concept, the redistribution linesmay be formed of, but is not limited to, the same material as thematerial that forms the TSVs 42.

Referring back to FIG. 1, a semiconductor chip is mounted on the wafer(operation S110). Specifically, referring to FIGS. 4 and 5, asemiconductor chip 130 is mounted on the upper area 40 of the wafer 10.Here, the semiconductor chip 130 may be mounted on each of the unitwafers UW as shown in FIG. 4.

In some embodiments of the present inventive concept, the semiconductorchip 130 may be mounted on the wafer 10 in the form of a flip-chip.Here, the top pads 56 in the redistribution layer 50 may be electricallyconnected to the semiconductor chip 130 by, for example, balls formedunder the semiconductor chip 130.

In some embodiments of the present inventive concept, the semiconductorchip 130 may be, for example, a logic semiconductor chip or a memorysemiconductor chip. The logic semiconductor chip may be amicroprocessor, such as a central processing unit (CPU), a controller,or an application specific integrated circuit (ASIC). The memorysemiconductor chip may be a volatile memory, such as a dynamic randomaccess memory (DRAM) or a static random access memory (SRAM), or anonvolatile memory such as a flash memory. In some other embodiments ofthe present inventive concept, the semiconductor chip 130 may be asemiconductor chip packaged by combining the above-described logicsemiconductor chips or memory semiconductor chips. That is, the type ofthe semiconductor chip 130 according to the current embodiment is notlimited to the above examples.

An underfill material 132 may be formed between the semiconductor chip130 and the wafer 10. The underfill material 132 protects the ballsformed under the semiconductor chip 130 and the top pads 56 of theredistribution layer 50 from the outside environment, thereby increasingreliability of electrical connection between the balls formed under thesemiconductor chip 130 and the top pads 56 of the redistribution layer50.

In the current embodiment, the semiconductor chip 130 may be smaller insize than each of the unit wafers UW. That is, a width W2 of thesemiconductor chip 130 may be smaller than a width W1 of each of theunit wafers UW.

Referring back to FIG. 1, a first passivation layer is formed to apredetermined thickness (operation S120). Specifically, referring toFIG. 6, a first passivation layer 150 is formed on the wafer 10 to apredetermined first thickness T1. The first thickness T may be athickness large enough to entirely cover the semiconductor chip 130 andto enable, in a subsequent process, the lower area 30 of the wafer 10 tobe removed in a state where no support is attached to the wafer 10.

The semiconductor chip 130 may be completely sealed with the firstpassivation layer 150. In some embodiments of the present inventiveconcept, the first passivation layer 150 may include a materialdifferent from the above-described underfill material 132. However, thepresent inventive concept is not limited thereto. In some otherembodiments of the present inventive concept, the first passivationlayer 150 may include the same material as the above-described underfillmaterial 132.

Referring back to FIG. 1, TSVs placed in an upper area of the wafer areexposed (operation S130). Specifically, referring to FIG. 7, the TSVs 42placed in the upper area 40 of the wafer 10 are exposed by removing thelower area 30 of the wafer 10. In the current embodiment, the lower area30 of the wafer 10 is removed in a state where no support is attached tothe wafer 10. The lower area 30 of the wafer 10 can be removed in thestate where no support is attached to the wafer 10 because the firstpassivation layer 150 was formed to the first thickness T1 (see FIG. 6)which is large enough to negate the need for a support.

If no support is required in the process of exposing the TSVs 42 byremoving the lower area 30 of the wafer 10, glue is not also required toattach a support to the wafer 10. Therefore, costs can be saved in theprocess of fabricating a semiconductor package 1 (see FIG. 13), andprocess speed of fabricating a semiconductor package can be improved.

The lower area 30 of the wafer 10 may be removed by, but is not limitedto, mechanical polishing, chemical mechanical polishing (CMP), or aseparation method, such as smart cut, which separates the lower area 30from the wafer 10 by forming a weak layer in the wafer 10.

Referring back to FIG. 1, connection terminals including bottom pads andbumps are formed on a bottom surface of the wafer (operation S140).Specifically, referring to FIG. 8, bottom pads 123 electricallyconnected to the TSVs 42 are formed in regions of a bottom surface ofthe wafer 10 in which the TSVs 42 are exposed. Then, bumps 128 areformed to be electrically connected to the bottom pads 123. The bumps128 may be solder balls and may be attached to the bottom pads 123 by athermocompression bonding process and/or a reflow process.

Referring back to FIG. 1, a top surface of the semiconductor chip isexposed by partially removing the first passivation layer (operationS150). Specifically, referring to FIG. 9, a portion of the firstpassivation layer 150 disposed on a top surface of the semiconductorchip 130 is removed, thereby exposing the top surface of thesemiconductor chip 130.

The first passivation layer 150 may be partially removed by, e.g., CMP.Here, the bottom pads 123 and the bumps 128 formed on the bottom surfaceof the wafer 10 may be protected with a protective tape. That is, theprotective tape may be attached to the bottom pads 123 and the bumps 128formed on the bottom surface of the wafer 10 in order to protect thebottom pads 123 and the bumps 128. In this state, the first passivationlayer 150 may be partially removed by, for example, CMP.

The partial removal of the first passivation layer 150 may result in areduction in the thickness of the first passivation layer 150 from thefirst thickness T1 (see FIG. 6) to a second thickness T2.

In some embodiments of the present inventive concept, the upper area 40of the semiconductor chip 130 may be partially removed in the process ofpartially removing the first passivation layer 150. As a result, thesemiconductor chip 130 may be thinned. In some other embodiments of thepresent inventive concept, the topmost surface of the semiconductor chip130 and the topmost surface of the first passivation layer 150 may bemade to lie in the same plane by the removal of the first passivationlayer 150.

Referring back to FIG. 1, the wafer may be sawed (operation S160).Specifically, referring to FIG. 10, the wafer 10 is sawed along thescribing line 12, thereby separating the unit wafers UW from each other.Each of the unit wafers UW separated from each other may be onesub-package on which the semiconductor chip 130 is mounted. The sawingprocess may be performed using a cutter 60 as shown in the drawing, orby using a laser.

Referring back to FIG. 1, a sub-package is mounted on a printed circuitboard (PCB), and a second passivation layer is formed (operation S170).Specifically, referring to FIGS. 11 and 12, a sub-package obtained bysawing the wafer 10 may be mounted on a PCB 110 such that the bumps 128of the sub-package are electrically connected to top pads 112 of the PCB110. The top pads 112 may be electrically connected to bottom pads 114by distribution lines included in the PCB 110.

A second passivation layer 170 may be formed on the PCB 110 to seal thesub-package. The second passivation layer 170 may be formed to cover thebottom, side, and top surfaces of the sub-package, as shown in thedrawings.

The second passivation layer 170 may include an insulating material. Insome embodiments of the present inventive concept, the secondpassivation layer 170 may include a material different from the firstpassivation layer 150. However, the present inventive concept is notlimited thereto. In some other embodiments of the present inventiveconcept, the second passivation layer 170 may include the same materialas the first passivation layer 150.

The PCB 110 may include a plurality of unit PCBs UP as shown in FIG. 11,and one sub-package may be mounted on each of the unit PCBs UP. The PCB110 may be formed by forming a printed circuit of a predetermined shapeon a substrate made of glass, ceramic, plastic, etc. However, thepresent inventive concept is not limited to this example.

Referring back to FIG. 1, solder balls are formed on the PCB (operationS180). Specifically, referring to FIG. 13, solder balls 116 electricallyconnected to the bottom pads 114 of the PCB 110 may be formed on abottom surface of the PCB 110. The solder balls 116 may be formed as agrid array such as a pin grid array, a ball grid array or a land gridarray.

With the formation of the solder balls 116 on the bottom surface of thePCB 110, the semiconductor chip 130 can be electrically connected to anexternal device by the top pads 56 included in the redistribution layer50, the redistribution lines included in the redistribution layer 50,the TSVs 42, the bottom pads 123 formed on the bottom surface of thewafer 10, the bumps 128, the top and bottom pads 112 and 114 of the PCB110, the solder balls 116, etc.

Referring back to FIG. 1, the PCB may be sawed (operation S190). As aresult of sawing the PCB 110 into the unit PCBs UP, the semiconductorpackage 1 as shown in FIG. 13 may be fabricated.

A method of fabricating a semiconductor package according to anotherembodiment of the present inventive concept will now be described withreference to FIGS. 14 through 16.

FIGS. 14 through 16 are views illustrating operations of a method offabricating a semiconductor package according to another embodiment ofthe present inventive concept. The current embodiment will hereinafterbe described, focusing mainly on differences with the perviousembodiment.

Referring to FIG. 14, in the method of fabricating a semiconductorpackage according to the current embodiment, a semiconductor chip 130may be larger in size than a unit wafer UW. That is, a width W2 of thesemiconductor chip 130 may be greater than a width W1 of the unit waferUW.

In this case, an underfill material 132 may be formed to a width greaterthan the width W1 of the unit wafer UW, as shown in the drawing. Theunderfill material 132 protects balls formed under the semiconductorchip 130 and top pads 56 of a redistribution layer 50 from the outsideenvironment, thereby increasing reliability of electrical connectionbetween the balls formed under the semiconductor chip 130 and the toppads 56 of the redistribution layer 50.

In the current embodiment, the orientation of the unit wafer UW ischanged. Accordingly, relative positions of an upper area 40 and a lowerarea 30 in the previous embodiment are changed. That is, in the currentembodiment, the lower area 30 may be placed on the upper area 40.

Referring to FIG. 15, since the semiconductor chip 130 is larger in sizethan the unit wafer UW in the current embodiment, a first passivationlayer 150 may be formed to entirely cover the unit wafer UW. Here, athird thickness T3 of the first passivation layer 150 may be a thicknesslarge enough to enable, in a subsequent process, the lower area 30 ofthe unit wafer UW to be removed in a state where no support is attachedto the unit wafer UW.

Referring to FIG. 16, TSVs 42 placed in the upper area 40 of a wafer 10are exposed by removing the lower area 30 of the wafer 10. In thecurrent embodiment, the lower area 30 of the wafer 10 is removed in astate where no support is attached to the wafer 10. The lower area 30 ofthe wafer 10 can be removed in the state where no support is attached tothe wafer 10 because the first passivation layer 150 was formed to thethird thickness T3 (see FIG. 15) which is large enough to negate theneed for a support.

Subsequently, the fabrication process according to the previousembodiment may be performed to produce a semiconductor package 2 asshown in FIG. 17. Here, processes performed can be fully inferred fromthe previous embodiment by those of ordinary skill in the art to whichthe present inventive concept pertains, and thus a repetitivedescription thereof will be omitted.

A method of fabricating a semiconductor package according to anotherembodiment of the present inventive concept will now be described withreference to FIGS. 18 and 19.

FIGS. 18 and 19 are views illustrating operations of a method offabricating a semiconductor package according to another embodiment ofthe present inventive concept. The current embodiment will hereinafterbe described, focusing mainly on differences with the previousembodiments.

Referring to FIG. 18, the current embodiment is different from theprevious embodiments in that through vias 200 electrically connected topower/ground pads 136 of a semiconductor chip 130 are additionallyformed in the current embodiment when TSVs 42 placed in an upper area 40of a wafer 10 are exposed by removing a lower area 30 of the wafer 10.

While the through vias 200 electrically connected to the power/groundpads 136 of the semiconductor chip 130 are illustrated in FIG. 18, thepresent inventive concept is not limited thereto. In some embodiments ofthe present inventive concept, the through vias 200 may be replaced byjoint balls.

Subsequently, the fabrication processes according to the previousembodiments may be performed to produce a semiconductor package 3 asshown in FIG. 19. Here, the through vias 200 may be electricallyconnected to the outside (for example, a power/ground terminal) of thesemiconductor package 3 by being electrically connected to, e.g., solderballs 116 as shown in the drawing. Other processes necessary tofabricate the semiconductor package 3 according to the currentembodiment can be fully inferred from the previous embodiments by thoseof ordinary skill in the art to which the present inventive conceptpertains, and thus a repetitive description thereof will be omitted.

FIG. 20 is a schematic diagram illustrating a memory card 800 to whichsemiconductor packages according to embodiments of the present inventiveconcept are applied.

Referring to FIG. 20, the memory card 800 may include a controller 820and a memory 830 in a housing 810. The controller 820 and the memory 830may exchange electrical signals. In an example, the memory 830 and thecontroller 820 may exchange data according to a command of thecontroller 820. Accordingly, the memory card 800 may store data in thememory 830 or output data from the memory 830.

The controller 820 or the memory 830 may include semiconductor packagesaccording to embodiments of the present inventive concept. In anexample, the controller 820 may include a system in package (SIP), andthe memory 830 may include a multi-chip package (MCP). The controller820 and/or the memory 830 may be provided as a stack package (SP).

The memory card 800 may be used as a data storage medium of variousportable devices. Examples of the memory card 800 may include amultimedia card (MMC) and a secure digital (SD) card.

FIG. 21 is a block diagram of an electronic system 900 to whichsemiconductor packages according to embodiments of the present inventiveconcept are applied.

Referring to FIG. 21, the electronic system 900 may employ thesemiconductor packages according to the above-described embodiments ofthe present inventive concept. Specifically, the electronic system 900may include a memory system 912, a processor 914, a RAM 916 and a userinterface 918.

The memory system 912, the processor 914, the RAM 916 and the userinterface 917 may communicate data with each other via a bus 920.

The processor 914 may execute programs, and may control the electronicsystem 900. The RAM 916 may be used as an operating memory for theprocessor 914. The processor 914 and the RAM 916 may be packaged into asingle semiconductor device or a semiconductor package using the methodsof fabricating a semiconductor package according to the above-describedembodiments of the present inventive concept.

The user interface 918 may be used to input data to or output data fromthe electronic system 900.

The memory system 912 may include a controller to drive the memorysystem 912, and may also include an error correction block. The errorcorrection block may be configured to detect error from data present inthe memory system 912 by means of error correction code (ECC) and tocorrect the detected error.

The memory system 912 may be integrated into a single semiconductordevice. The memory system 912 may be integrated into a singlesemiconductor device so as to form a memory card. In an example, thememory system 912 may be integrated into a single semiconductor deviceso as to form a memory card such as a PC memory card internationalassociation (PCMCIA) card, a compact flash (CF) card, a smart media (SM)card such as SMC), a memory stick, a multimedia card (MMC) (such asRS-MMC or MMCmicro), a secure digital (SD) card (such as miniSD, microSCor SDHC), or a universal flash storage (UFS).

The electronic system 900 of FIG. 21 may be applied to electroniccontrol devices for various electronic devices. FIG. 22 is a diagramillustrating an example of the application of the electronic system 900of FIG. 21 to a smartphone 1000. In a case in which the electronicsystem 900 of FIG. 21 is applied to the smartphone 1000, the electronicsystem 900 of FIG. 21 may be, but is not limited to, an applicationprocessor (AP).

The electronic system 900 of FIG. 21 may be provided as a computer, anUltra Mobile PC (UMPC), a work station, a net-book computer, a PersonalDigital Assistant (PDA), a portable computer, a web tablet, a wirelessphone, a mobile phone, a smart phone, an e-book, a portable multimediaplayer (PMP), a portable game console, a navigation device, a black box,a digital camera, a 3-dimensional television set, a digital audiorecorder, a digital audio player, a digital picture recorder, a digitalpicture player, a digital video recorder, a digital video player, adevice capable of transmitting and receiving data in a wirelessenvironment, one of a variety of electronic devices that constitute ahome network, one of a variety of electronic devices that constitute acomputer network, one of a variety of electronic devices that constitutea telematics network, a radio frequency identification (RFID) device, orone of a variety of electronic devices that constitute a computingsystem.

Although a few embodiments of the present general inventive concept havebeen shown and described, it will be appreciated by those skilled in theart that changes may be made in these embodiments without departing fromthe principles and spirit of the general inventive concept, the scope ofwhich is defined in the appended claims and their equivalents.

What is claimed is:
 1. A method of fabricating a semiconductor package,the method comprising: providing a wafer which comprises an upper areahaving through silicon vias (TSVs) and a lower area not having the TSVs;mounting a semiconductor chip on the upper area of the wafer; forming apassivation layer to a predetermined thickness to cover thesemiconductor chip; exposing the TSVs by removing the lower area of thewafer in a state where no support is attached to the wafer; and exposinga top surface of the semiconductor chip by partially removing thepassivation layer.
 2. The method of claim 1, further comprising: formingconnection terminals, which are electrically connected to the exposedTSVs, on a bottom surface of the wafer before the exposing of the topsurface of the semiconductor chip by partially removing the passivationlayer.
 3. The method of claim 2, wherein the connection terminalscomprise bottom pads and bump balls.
 4. The method of claim 2, whereinthe connection terminals are protected with a protective tape when thetop surface of the semiconductor chip is exposed by partially removingthe passivation layer.
 5. The method of claim 2, further comprising,after the exposing of the top surface of the semiconductor chip,:forming sub-packages by sawing the wafer into a plurality of unitwafers; and mounting the sub-packages on a printed circuit board (PCB).6. The method of claim 5, further comprising: forming semiconductorpackages by sawing the PCB after the mounting of the sub-packages on thePCB.
 7. The method of claim 1, wherein the mounting of the semiconductorchip comprises mounting the semiconductor chip in the form of aflip-chip.
 8. The method of claim 7, wherein the wafer further comprisestop pads which are electrically connected to the semiconductor chip anda redistribution layer which electrically connects the TSVs and the toppads through redistribution lines included therein.
 9. The method ofclaim 1, wherein the wafer comprises a plurality of unit wafers, whereineach of the unit wafers is wider than the semiconductor chip.
 10. Themethod of claim 1, wherein the wafer comprises a plurality of unitwafers, wherein each of the unit wafers is narrower than thesemiconductor chip.
 11. The method of claim 10, further comprisingforming through vias which penetrate the passivation layer and areelectrically connected to the semiconductor chip.
 12. A method offabricating a semiconductor package, the method comprising: providing awafer which comprises an upper area having TSVs and a lower area nothaving the TSVs; mounting a semiconductor chip on the upper area of thewafer; forming a passivation layer to a predetermined thickness to coverthe semiconductor chip; exposing the TSVs by removing the lower area ofthe wafer in a state where no support is attached to the wafer; formingbottom pads and bump balls, which are electrically connected to theexposed TSVs, on a bottom surface of the wafer; and exposing a topsurface of the semiconductor chip by partially removing the passivationlayer.
 13. The method of claim 12, wherein the exposing of the TSVs byremoving the lower area of the wafer comprises exposing the TSVs byremoving the lower area of the wafer in the state where no support isattached to the wafer.
 14. The method of claim 12, wherein the waferfurther comprises top pads which are arranged at a first interval and aredistribution layer which electrically connects the TSVs and the toppads through redistribution lines included therein, and the TSVs arearranged at a second interval different from the first interval.
 15. Themethod of claim 14, wherein the first interval is smaller than thesecond interval.
 16. A method of fabricating a semiconductor package,the method comprising: providing a wafer which comprises a first areahaving through silicon vias (TSVs) and a second area not having theTSVs; mounting a semiconductor chip on the first area of the wafer, thesemiconductor chip being wider than the wafer to extend beyond sidesthereof; forming a passivation layer to a predetermined thickness tocover the wafer and exposed portions of the semiconductor chip extendingbeyond the wafer; and exposing the TSVs by removing the second area ofthe wafer and corresponding portion of the passivation layer in a statewhere no support is attached to the wafer.
 17. The method of claim 16,further comprising: forming through vias in the remaining passivationlayer to be electrically connected to power/ground pads of thesemiconductor chip when the through vias in the first area are beingexposed.
 18. The method of claim 17, further comprising: formingconnection terminals to be electrically connected to the exposed TSVs ona bottom surface of the wafer; and forming connection terminals to beelectrically connected to the exposed through vias of the passivationlayer.
 19. The method of claim 16, wherein the mounting of thesemiconductor chip comprises mounting the semiconductor chip in the formof a flip-chip.
 20. The method of claim 19, wherein the wafer comprises:top pads which are electrically connected to the semiconductor chip; anda redistribution layer which electrically connects the TSVs and the toppads through redistribution lines included therein.